Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication reference clock frequency various applications through an edge combiner (EC). A simpler structure more sensitive process, voltage, temperature (PVT), so DLL complements itself quickly in feedback system improves stability final output. The proposed DLL-based multiplier can prevent harmonic lock generation using first phase canceller (FPC), thus compensating faster time. circuit built with 55 nm CMOS process has chip area 0.0225 mm2. design achieves total power consumption 0.48 mW at 30.72 MHz operating frequency, duty also operate stably from 15 75%.